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3.1.3.8
Baud Rate Selection Bit (BAUD)
The baud rate selection bit selects one of two PSI5 baud rates as shown below. Reference Section 2.6 for baud rate timing
specifications.
BAUD
0
1
Baud Rate
Low Baud Rate (125 kBaud)
High Baud Rate (190.5 kBaud)
3.1.4
Device Configuration Registers (DEVCFG3, DEVCFG4, DEVCFG5)
Device configuration registers 3, 4, and 5 are user programmable OTP registers which contain device configuration informa-
tion.
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$06
DEVCFG3
TRANS_MD[1]
TRANS_MD[0]
LPF[1]
LPF[0]
TIMESLOTB[9] TIMESLOTB[8] TIMESLOTA[9] TIMESLOTA[8]
$07
$08
DEVCFG4
DEVCFG5
TIMESLOTA[7] TIMESLOTA[6] TIMESLOTA[5] TIMESLOTA[4] TIMESLOTA[3] TIMESLOTA[2] TIMESLOTA[1] TIMESLOTA[0]
TIMESLOTB[7] TIMESLOTB[6] TIMESLOTB[5] TIMESLOTB[4] TIMESLOTB[3] TIMESLOTB[2] TIMESLOTB[1] TIMESLOTB[0]
Factory Default
0
0
0
0
0
0
0
0
3.1.4.1
PSI5 Transmission Mode Selection Bits (TRANS_MD[1:0])
The PSI5 transmission mode selection bits select the PSI5 transmission mode as shown below.
TRANS_MD[1]
0
0
1
1
TRANS_MD[0]
0
1
0
1
Operating Mode
Normal Mode (Asynchronous or Parallel, Synchronous)
Synchronous Double Sample Rate Mode
16-bit Resolution Mode (2 10-bit Responses)
Daisy Chain Mode
Reference
Section 4.5.1
Section 4.5.1.3
Section 4.5.2
Section 4.5.4
3.1.4.2
Low-Pass Filter Selection Bit (LPF[1:0])
The low-pass filter selection bits select the low-pass filter for the acceleration signal as described below:
LPF[1]
0
0
1
1
LPF[0]
0
1
0
1
Low-Pass Filter Selected
400 Hz, 3-Pole
400 Hz, 4-Pole
Reserved
Reserved
3.1.4.3
TimeSlot Selection Bits (TIMESLOTx[9:0])
The timeslot selection bits select the time slot(s) to be used for data transmission. Reference Section 4.5 for details regarding
PSI5 transmission modes and time slots. Accepted time slot values are 0.5 μ s to 511.5 μ s in 0.5 μ s increments. Care must be
taken to prevent from programming time slots which violate the PSI5 Version 1.3 specification, or time slots which will cause data
contention.
TIMESLOTx[9:0]
00 0000 0000
Non-Zero
ASYNC Bit
0
1
N/A
Time Slot
Default Time Slot (t TIMESLOT_DFLT ) from start of Sync Pulse (t TRIG )
Asynchronous Mode
TimeSlot Definition from start of Sync Pulse (t TRIG ) in 0.5 μ s Increments
Reference
Section 4.5
Section 4.5.1.1
Section 4.5
Note: TIMESLOTB is only used for Synchronous Double Sample Rate Mode and 16-Bit Resolution Mode.
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
15
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